1 idt74fct163373a/c 3.3v cmos 16-bit transparent latch industrial temperature range october 2008 industrial temperature range the idt logo is a registered trademark of integrated device technology, inc. ? 2002 integrated device technology, inc. dsc-5416/5 features: ? 0.5 micron cmos technology ? typical t sk(o) (output skew) < 250ps ? esd > 2000v per mil-std-883, method 3015; > 200v using machine model (c = 200pf, r = 0) ?v cc = 3.3v 0.3v, normal range, or v cc = 2.7v to 3.6v, extended range ? cmos power levels (0.4 w typ. static) ? rail-to-rail output swing for increased noise margin ? low ground bounce (0.3v typ.) ? inputs (except i/o) can be driven by 3.3v or 5v components ? available in ssop and tssop packages functional block diagram idt74fct163373a/c 3.3v cmos 16-bit transparent latch description: the fct163373 16-bit transparent d-type latches are built using advanced dual metal cmos technology. these high-speed, low-power latches are ideal for temporary storage of data. they can be used for implementing memory address latches, i/o ports, and bus drivers. the output enable and latch enable controls are organized to operate each device as two 8-bit latches or one 16-bit latch. flow-through organization of signal pins simplifies layout. all inputs are designed with hysteresis for improved noise margin. the inputs of fct163373 can be driven from either 3.3v or 5v devices. this feature allows the use of these transparent latches as translators in a mixed 3.3v/5v supply system. with xle inputs high, the fct163373 can be used as a buffer to connect 5v components to a 3.3v bus. 2 o 1 2 oe 2 le 2 d 1 to seven other channels c d 1 oe 1 le 1 o 1 1 d 1 to seven other channels c d 1 48 47 2 24 25 36 13
2 industrial temperature range idt74fct163373a/c 3.3v cmos 16-bit transparent latch symbol description max unit v term (2) terminal voltage with respect to gnd ?0.5 to +4.6 v v term (3) terminal voltage with respect to gnd ?0.5 to 7 v v term (4) terminal voltage with respect to gnd ?0.5 to v cc +0.5 v t stg storage temperature ?65 to +150 c i out dc output current ?60 to +60 ma absolute maximum ratings (1) notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. vcc terminals. 3. input terminals. 4. outputs and i/o terminals. symbol parameter (1) conditions typ. max. unit c in input capacitance v in = 0v 3.5 6 pf c out output capacitance v out = 0v 3.5 8 pf capacitance (t a = +25c, f = 1.0mhz) note: 1. this parameter is measured at characterization but not tested. pin configuration ssop/ tssop top view pin names description x d x data inputs xle latch enable input (active high) x oe output enable input (active low) x o x 3-state outputs pin description function table (1) inputs outputs xdx xle x oe xbx hhl h lhl l xll o (2) xxh z notes: 1. h = high voltage level l = low voltage level x = don?t care z = high-impedance 2. output level before the indicated steady-state input conditions were established. 1 o 1 gnd 1 o 3 v cc 1 oe gnd 2 o 2 gnd v cc gnd 1 o 2 1 o 4 1 o 5 1 o 6 1 o 7 1 o 8 2 o 1 2 o 3 2 o 4 2 o 5 2 o 7 2 o 8 2 o 6 2 oe 1 le 1 d 1 1 d 2 gnd 1 d 3 1 d 4 v cc 1 d 5 1 d 6 1 d 7 1 d 8 2 d 1 2 d 2 2 d 3 2 d 4 v cc 2 d 5 2 d 7 2 d 8 2 d 6 2 le gnd gnd gnd 39 29 30 31 32 33 34 35 36 37 38 25 26 27 28 48 47 41 42 43 44 45 46 40 1 2 3 4 5 6 7 8 9 10 12 13 14 15 16 17 18 19 20 11 21 22 23 24
3 idt74fct163373a/c 3.3v cmos 16-bit transparent latch industrial temperature range symbol parameter test conditions (1) min. typ. (2) max. unit v ih input high level (input pins) guaranteed logic high level 2 ? 5.5 v input high level (i/o pins) 2 ? v cc +0.5 v il input low level (input and i/o pins) guaranteed logic low level ?0.5 ? 0.8 v i ih input high current (input pins) v cc = max. v i = 5.5v ? ? 1 input high current (i/o pins) v i = v cc ?? 1a i il input low current (input pins) v i = gnd ? ? 1 input low current (i/o pins) v i = gnd ? ? 1 i ozh high impedance output current v cc = max. v o = v cc ?? 1a i ozl (3-state output pins) v o = gnd ? ? 1 v ik clamp diode voltage v cc = min., i in = ?18ma ? ?0.7 ?1.2 v i odh output high current v cc = 3.3v, v in = v ih or v il, v o = 1.5v (3) ?36 ?60 ?110 ma i odl output low current v cc = 3.3v, v in = v ih or v il, v o = 1.5v (3) 50 90 200 m a v oh output high voltage v cc = min. i oh = ?0.1ma v cc -0.2 ? ? v in = v ih or v il i oh = ?3ma 2.4 3 ? v v cc = 3v i oh = ?8ma 2.4 (5) 3? v in = v ih or v il v ol output low voltage v cc = min. i ol = 0.1ma ? ? 0.2 v in = v ih or v il i ol = 16ma ? 0.2 0.4 i ol = 24ma ? 0.3 0.55 v v cc = 3v i ol = 24ma ? 0.3 0.5 v in = v ih or v il i os short circuit current (4) v cc = max., v o = gnd (3) ?60 ?135 ?240 ma v h input hysteresis ? ? 150 ? mv i ccl quiescent power supply current v cc = max. ? 0.1 10 a i cch v in = gnd or v cc i ccz dc electrical characteristics over operating range following conditions apply unless otherwise specified: industrial: t a = ?40c to +85c, v cc = 2.7v to 3.6v notes: 1. for conditions shown as min. or max., use appropriate value specified under electrical characteristics for the applicable dev ice type. 2. typical values are at v cc = 3.3v, +25c ambient. 3. not more than one output should be shorted at one time. duration of the test should not exceed one second. 4. this parameter is guaranteed but not tested. 5. v oh = v cc ?0.6v at rated current.
4 industrial temperature range idt74fct163373a/c 3.3v cmos 16-bit transparent latch power supply characteristics symbol parameter test conditions (1) min. typ. (2) max. unit i cc quiescent power supply v cc = max. ? 2 30 a current ttl inputs high v in = v cc ?0.6v (3) i ccd dynamic power supply current (4) v cc = max. v in = v cc ? 50 75 a/ outputs open v in = gnd mhz x oe = gnd one input toggling 50% duty cycle i c total power supply current (6) v cc = max., outputs open v in = v cc ? 0.5 0.8 ma f i = 10mhz v in = gnd 50% duty cycle x oe = gnd xle = v cc v in = v cc ?0.6v ? 0.5 0.8 one bit toggling v in = gnd v cc = max., outputs open v in = v cc ?2 3 (5) f i = 2.5mhz v in = gnd 50% duty cycle x oe = gnd v in = v cc ?0.6v ? 2 3.3 (5) xle = v cc v in = gnd sixteen bits toggling notes: 1. for conditions shown as max. or min., use appropriate value specified under electrical characteristics for the applicable dev ice type. 2. typical values are at v cc = 3.3v, +25c ambient. 3. per ttl driven input; all other inputs at v cc or gnd. 4. this parameter is not directly testable, but is derived for use in total power supply calculations. 5. values for these conditions are examples of the i cc formula. these limits are guaranteed but not tested. 6. i c = i quiescent + i inputs + i dynamic i c = i cc + di cc d h n t + i ccd (f cp n cp /2 + fini) i cc = quiescent current (i ccl, i cch and i ccz ) i cc = power supply current for a ttl high input d h = duty cycle for ttl inputs high n t = number of ttl inputs at d h i ccd = dynamic current caused by an input transition pair (hlh or lhl) f cp = clock frequency for register devices (zero for non-register devices) n cp = number of clock inputs at f cp f i = input frequency n i = number of inputs at fi
5 idt74fct163373a/c 3.3v cmos 16-bit transparent latch industrial temperature range fct163373a fct163373c symbol parameter condition (2) min. (3) max. min. (3) max. unit t plh propagation delay c l = 50pf 1.5 5.2 1.5 4.2 ns t phl xdx to xox r l = 500 t plh propagation delay 2 8.5 2 5.5 ns t phl xle to xox t pzh output enable time 1.5 6.5 1.5 5.5 ns t pzl t phz output disable time 1.5 5.5 1.5 5 ns t plz t su set-up time high or low, xdx to xle 2 ? 2 ? ns t h hold time high or low, xdx to xle 1.5 ? 1.5 ? ns t w xle pulse width high 5 ? 5 ? ns t sk (o) output skew (4) ? 0.5 ? 0.5 ns switching characteristics over operating range (1) notes: 1. propagation delays and enable/disable times are with v cc = 3.3v 0.3v, normal range. for v cc = 2.7v to 3.6v, extended range, all propagation delays and enable/disable times should be degraded by 20%. 2. see test circuit and waveforms. 3. minimum limits are guaranteed but not tested on propagation delays. 4. skew between any two outputs, of the same package, switching in the same direction. this parameter is guaranteed by design.
6 industrial temperature range idt74fct163373a/c 3.3v cmos 16-bit transparent latch pulse generator r t d.u.t. v cc v in c l v out 50pf 500 500 open gnd 6v 3v 1.5v 0v 3v 1.5v 0v 3v 1.5v 0v 3v 1.5v 0v data input timing input asynchronous control preset clear etc. synchronous control t su t h t rem t su t h preset clear clock enable etc. high-low-high pulse low-high-low pulse t w 1.5v 1.5v same phase input transition 3v 1.5v 0v 1.5v v oh t plh output opposite phase input transition 3v 1.5v 0v t plh t phl t phl v ol control input 3v 1.5v 0v 3v 0v output normally low output normally high switch 6v switch gnd v ol 0.3v 0.3v t plz t pzl t pzh t phz 3v 0v 1.5v 1.5v enable disable v oh test circuits and waveforms propagation delay test circuits for all outputs enable and disable times set-up, hold, and release times pulse width test switch open drain disable low 6v enable low disable high gnd enable high all other tests open switch position definitions: c l = load capacitance: includes jig and probe capacitance. r t = termination resistance: should be equal to z out of the pulse generator. notes: 1. diagram shown for input control enable-low and input control disable-high. 2. pulse generator for all pulses: rate
7 idt74fct163373a/c 3.3v cmos 16-bit transparent latch industrial temperature range ordering information xx temp. range xxxx device type x package pv pvg pa pag shrink small outline package ssop - green thin shrink small outline package tssop - green ? 40 c to +85 c 74 fct xxx family 163 double-density 3.3volt 373a 373c non-inverting 16-bit transparent latch corporate headquarters for sales: for tech support: 6024 silver creek valley road 800-345-7015 or 408-284-8200 logichelp@idt.com san jose, ca 95138 fax: 408-284-2775 www.idt.com
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